This invention relates to a method and a circuit for minimizing glitches in phase-locked loops.
A PLL (Phase Lock Loop) as generally shown at 1 in FIG. 1 comprises essentially a phase comparator 2, a filter 3, a frequency divider 4, and a voltage controlled oscillator VCO 5. With the phase lock loop PLL 1 locked to a periodic input signal at a frequency Fref, a frequency Fvco of the voltage controlled oscillator VCO 5 is equal to that of the input signal multiplied by a division ratio N of the frequency divider 4.
The phase comparator 2 then generates a signal which is proportional to the phase difference between the input signal and the output signal of the frequency divider 4. This signal modifies, through the filter 3, the control voltage of the voltage controlled oscillator VCO 5, and consequently its frequency Fvco as well, thereby bringing the output frequency Fdiv of the frequency divider 4 to the same value as the input frequency Fref.
The characteristic parameters according to which a phase lock loop PLL 1 is evaluated are:
accuracy of the generated frequency;
phase noise;
glitch rejection;
locking time; and
loop phase margin.
The frequency accuracy of the voltage controlled oscillator VCO 5 is dependent on the frequency accuracy of the input signal and the accuracy of the phase comparator 2.
Specifically, it is:
xcex94Fvco=N*xcex94Fref+xcex94"PHgr"/2*xcfx80*Fvcoxe2x80x83xe2x80x83(1)
where,
xcex94Fvco is the frequency error of the voltage controlled oscillator VCO 5;
N is the division ratio of the frequency divider 4;
xcex94Fref is the frequency error of the input signal;
xcex94"PHgr" is the phase error of the phase comparator 2; and
Fvco is the output frequency of the voltage controlled oscillator VCO 5.
System specifications covering certain communication standards provide for the largest frequency error of the voltage controlled oscillator VCO 5 to be in the 10xe2x88x928*Fvco range. For example, the GSM Standard sets the maximum error to 2*10xe2x88x928*Fvco.
In this case, assuming one half of that frequency error to be due to inaccuracy of the input frequency (usually obtained from a crystal oscillator), the maximum acceptable phase error would be 6*10xe2x88x928 radians.
Such a restricted value for the phase error rules out the use a Gilbert cell for a phase comparator, since this cell exhibits a minimum phase error which lies well above said limit. Furthermore, a Gilbert cell type of phase comparator would exhibit a non-constant system loop gain in the phase locked range of operation.
Thus, for standard practical applications, the phase comparator is provided in a charge pump form, using first Icharge and second Idischarge current generators, having the same Icp value and opposite signs, which generators will vary the output control voltage in opposite directions according to whether the output signal of the frequency divider 4 is leading or lagging behind the input signal. A block diagram for a phase lock loop PLL 1xe2x80x2 including a charge pump 6, according to the prior art, is shown in FIG. 2.
To avoid phase errors and variations in the loop gain of the phase lock loop PLL 1xe2x80x2 near the locking range, a time interval Tmin is usually provided when both current generators, Icharge and Idischarge, deliver equal and opposite currents, such that the input voltage to the filter 3 will remain unchanged, as shown in FIG. 3. Thus, the current generators Icharge, Idischarge are turned on at each cycle to ensure that the frequency of the voltage controlled oscillator VCO 5 remains locked to the value N*Fref.
The use of a filter 3xe2x80x2 with two-poles and a zero, as schematically illustrated in FIG. 4, is conceivable. This filter 3xe2x80x2 comprises a resistive element R1 connected in series to a first capacitive element C1, between a terminal T1 and a voltage reference such as a ground GND. The filter 3xe2x80x2 also comprises a second capacitive element C2, connected between said terminal T1 and ground, in parallel with said resistive element R1 and said first capacitive element C1.
The settling time is dependent on the overall loop gain, its phase margin, the filter size, and the maximum admissible frequency error.
Using the filter 3xe2x80x2, it is readily seen that the proportionality of the settling time Ts is:                               T          ⁢                      xe2x80x83                    ⁢          s                ∝                                            N              *              R1              *              C1                                      I              ⁢                              xe2x80x83                            ⁢              cp              *              K              ⁢                              xe2x80x83                            ⁢              o                                *                      ln            ⁡                          (                              B                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  F                  ⁢                                      xe2x80x83                                    ⁢                  max                                            )                                                          (        2        )            
where,
N is the division ratio;
R1, C1 are elements of the filter 3xe2x80x2;
Icp is the charge pump 6 current;
Ko is the oscillator VCO 5 gain;
B is the channel jump of the oscillator VCO 5;
xcex94Fmax is the maximum frequency error of the oscillator VCO 5.
Formula (2) shows that to obtain short settling times, as is normally required, in wide band, small frequency error systems, it is necessary to use very high values for the charge pump 6 current and filters having decidedly small time constants.
Reasonable values for conventional systems of the GSM and DCS types are:
Icp=4 mA, and
t=25 xcexcs.
Thus, by suitable dimensioning of the filter and the charge pump, a phase lock loop PLL could be provided with a settling time value according to specification. However, such dimensioning would be at variance with the specified rejection of glitches at frequencies that are multiples of the reference frequency Fref of the phase lock loop PLL 1.
In fact, a real phase look loop PLL 1 would exhibit, as a result of process tolerances, a non-pure frequency spectrum, like that shown in FIG. 5.
In particular, the two most evident glitches locate a distance equal to the reference frequency Fref away from the lock frequency Fvco of the voltage controlled oscillator VCO 5. Other glitches, located farther from the oscillation frequency Fvco, are filtered and reduced to a large extent.
It should be noted that glitches are mainly due to two different phenomena, namely the leakage current of the VCO control terminal and a dissymmetry between the two generators of the charge pump.
In particular, the leakage current of the VCO control node is the sum of the leakage currents of the charge pump and the VCO. The contribution from the latter is generally dominant because, at the frequencies of interest, the VCO would essentially consist of an LC resonator, wherein the frequency variation is obtained by varying the voltage across a junction capacitance which has a fairly large leakage current.
The overall leakage current causes the control voltage of the VCO to change proportionally to that current, even with the VCO in the locked state, during the xe2x80x9coffxe2x80x9d period of the current generators of the charge pump. Consequently, at each cycle, the charge pump is to balance the amount of charge lost during the xe2x80x9coffxe2x80x9d period.
Thus, the control voltage waveform shows a periodic trend with a period 1/Fref, and this periodic signal generates glitches at frequencies that are multiples of the reference frequency Fref. It can be seen, therefore, that the amplitude of such glitches is directly proportional to the leakage current and inversely proportional to the value of the second capacitive element C2 of the filter 3xe2x80x2.
As a result, in transmission systems designed to strict specifications as to settling time and glitches, this contribution to the overall glitch requires that VCOs with very low associated leakage values be used. There are VCOs commercially available which meet both specifications for conventional transmission systems.
The generation of glitches is also due to asymmetry of the two generators of the charge pump. Particularly in the locked condition, in order to prevent the frequency of the VCO from varying, the average voltage value at the control node must be kept constant. The amounts of charge supplied by the two current generators must, therefore, be equal and opposite.
Assuming that in the locked condition one of the generators is delivering a current Icp for a time interval Tmin, and that the current error is xcex94Icp between the two generators, advantageously, the second generator would deliver a current Icp+xcex94Icp for a time interval equal to Tminxe2x88x92xcex94Tmin, to satisfy the following relation:
Icp*Tmin=(Icp+xcex94Icp)*(Tminxe2x88x92xcex94Tmin)xe2x80x83xe2x80x83(3)
Illustrated by way of example in FIG. 6 are waveforms representing the currents generated by the two current generators of the charge pump, as well as the difference between the two currents, equal to the current Ifiltro at the filter 3 in the locked condition.
In particular, it should be noted that the total amount of charge supplied to the filter 3 is zero, it being given as the difference of two identical values.
This current Ifiltro generates a periodic variation in the filter voltage, in turn generating glitches at frequencies that are multiples of the reference frequency Fref. These glitches are directly proportional to the asymmetry of the current generators, xcex94Icp, and the value of the xe2x80x9conxe2x80x9d period Tmin of the generators, and are inversely proportional to the filter capacitance C2.
The contribution to the generation of glitches from the asymmetry of the current generators in applications for which strict settling time specifications are provided, is an order of magnitude larger than the contribution from leakage.
Therefore, the requirements for settling time values and glitch generation are difficult to meet simultaneously, especially in transmission systems designed to strict specifications. In fact, whereas to obtain limited durations of the settling time a large charge current Icp must be used for the charge pump along with a very small filter capacitance C2, the error percent between the current generators, and the respective turn-on times, should be quite small.
Conventional circuit designs, and technological limitations setting a minimum turn-on time for a current generator, make meeting the specifications very difficult.
Embodiments of this invention provide a phase lock loop which can minimize the generation of glitches and overcome the limitations of prior art circuits so as to meet, for example, the specifications established for transmission systems.
These embodiments avoid direct connection of the charge pump to the filter, thereby suppressing the glitch due to asymmetry between the current generators of the phase comparator.
Specifically, the invention relates to a circuit for minimizing glitches in phase-locked loops, of the type having an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. In one embodiment, a compensation circuit is placed between the charge pump generator and the filter.
The features and advantages of the device and the method according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.